Digital filters, being well-suited for digital signal processing (DSP) applications, are being used in an increasing number of electronic systems. One commonly used type of digital filter is a finite impulse response (FIR) filter. The FIR filter is a sampled data filter that is characterized by its impulse response and comprises a number of tap coefficients or weights. Samples of an input signal V(t) are shifted into the FIR filter one sample per cycle. At each cycle t, the FIR filter computes the sum y(t):
      y    ⁡          (      t      )        =            ∑              i        =        0                    n        -        1              ⁢                  ⁢                  A        i            ·              V        ⁡                  (                      t            -            i                    )                    where, V(t−i) is a t−ith sample of input V(t), Ai is an ith tap coefficient of the FIR filter for 0≦i≦n−1 and n is the number of tap coefficients of the FIR filter.
Distributed arithmetic FIR filters are known to utilize less logic gates than digital FIR filters employing a transpose-form architecture. However, conventional transpose architecture FIR filters typically have less latency. Consequently, it would be desirable to create an improved distributed arithmetic digital FIR filter having a reduced latency.